Compact implementation of CCM and GCM modes of AES using DSP blocks Vrije Universiteit Brussel
In this manuscript, we have explored how the use of DSP
blocks in the implementation of two authenticated-encryption
modes of AES can optimize the PAR figures. Our results
reflect that a 20.98 % reduction in slice utilization can be
achieved at a throughput higher than 25 Mbps (12 MHz) in
the Artix-7 XC7A200TL FPGA.
blocks in the implementation of two authenticated-encryption
modes of AES can optimize the PAR figures. Our results
reflect that a 20.98 % reduction in slice utilization can be
achieved at a throughput higher than 25 Mbps (12 MHz) in
the Artix-7 XC7A200TL FPGA.