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A 42mW 230fs-Jitter Sub-sampling 60GHz PLL in 40nm CMOS
Boekbijdrage - Boekhoofdstuk Conferentiebijdrage
this paper presents the first mm-Wave PLL utilizing a subsampling
phase detector instead of a classical divider chain. Implemented in 40nm CMOS, the PLL has a jitter as low
as 230fs for a power consumption of 42mW.
phase detector instead of a classical divider chain. Implemented in 40nm CMOS, the PLL has a jitter as low
as 230fs for a power consumption of 42mW.
Boek: 2014 IEEE International Solid-State Circuits Conference
Series: 2014 IEEE International Solid-State Circuits Conference
Pagina's: 105-108
ISBN:978-1-4799-0920-9
Jaar van publicatie:2014
Trefwoorden:CMOS, PLL, sub-sampling, mm-wave