High-speed transmitter design for communication beyond 40 Gb/s

Nowadays, people are increasingly relying on the internet and expecting ever faster connectivity to either workplace or home. This poses increasingly challenging requirements for the network switches and core routers in the high speed data communication system. As an essential part of the network core routers, the access node terminates various user connections (such as: xDSL, GPON, 10GPON) and aggregates the data from many end-users. This data stream is forwarded at high speed along the optical fiber lines of the internet backbone. Today, however, data rates in industrial core routers are typically below 10 Gb/s per lane, which restricts the total capacity of the communication system. This research aims to greatly improve the data rate per lane beyond 40 Gb/s. Special measures are required in the transceiver electronics to overcome the problems caused by increasing data rate and the associated higher signal frequencies such as a larger amount of attenuation as well as inter-symbol interference (ISI) caused by the lossy traces on a printed circuit board (PCB). Otherwise, the signal waveform will be significantly distorted after travelling through the backplane interconnections. Therefore, an important part of the presented research focuses on the design of a digitally controlled equalization circuit based on a finite impulse response (FIR) filter structure to compensate for channel loss and to enhance the data rate by introducing pre-distortion of the transmitted signal waveform to diminish the inter-symbol interference effects.

Jaar van publicatie:2012