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Researcher
Arjun Singh
- Disciplines:Nanotechnology, Sensors, biosensors and smart sensors, Other electrical and electronic engineering, Design theories and methods
Affiliations
- Electronic Circuits and Systems (ECS) (Division)
Member
From1 Aug 2020 → 30 Nov 2018 - Electrical Energy Systems and Applications (ELECTA) (Division)
Member
From1 Aug 2020 → 31 Aug 2017 - ESAT - ELECTA, Electrical Energy and Computer Architectures (Division)
Member
From1 May 2014 → 31 Aug 2017 - ESAT - MICAS, Microelectronics and Sensors (Division)
Member
From6 Jun 2012 → 30 Nov 2018 - Sustainable Chemistry for Metals and Molecules (Division)
Member
From20 Jun 2011 → 23 Dec 2011
Publications
1 - 9 of 9
- Toward sub-20nm pitch Fin patterning and integration with DSA(2016)
Authors: Arjun Singh
Pages: 97790 - Next generation of decision making software for nanopatterns characterization: application to semiconductor industry(2016)
Authors: Arjun Singh
- Manufacturability of dense hole arrays with directed self-assembly using the CHIPS flow(2016)
Authors: Arjun Singh
Pages: 97770 - Hexagonal hole array patterning for memory applications(2015)
Authors: Arjun Singh
Pages: 623 - 629 - Patterning sub-25nm half-pitch hexagonal arrays of contact holes with chemo-epitaxial DSA guided by ArFi pre-patterns(2015)
Authors: Arjun Singh
Pages: 94250 - Impact of sequential infiltration synthesis on pattern fidelity of DSA lines(2015)
Authors: Arjun Singh, Ziad El Otell
Pages: 94250 - Using chemo-epitaxial directed self-assembly for repair and frequency multiplication of EUVL contact-hole patterns(2014)
Authors: Arjun Singh
- Readying directed self-assembly for patterning in semi-conductor manufacturing(2013)
Authors: Arjun Singh
Pages: 779 - 791 - Development and evaluation of a-SiC:H films using a dimethylsilacyclopentane precursor as a low -k Cu capping layer in advanced interconnects(2013)
Authors: Els Van Besien, Cong Wang, Patrick Verdonck, Arjun Singh, Yohan Barbarin, Marc Schaekers, Mikhaïl Baklanov, Sven Van Elshocht
Pages: 105 - 107
Patents
1 - 8 of 8
- Lithographic mask layer (Inventor)
- Metal of ceramic material hardened pattern (Inventor)
- Combined anneal and selective deposition process (Inventor)
- Method for patterning a substrate involving directed self-assembly (Inventor)
- Method for pattern formation on a substrate, associated semiconductor devices, and uses of the method (Inventor)
- Metal or ceramic material hardened pattern (Inventor)
- Method for manufacturing pillar or hole structures in a layer of a semiconductor device, and associated semiconductor structure (Inventor)
- METHOD FOR MANUFACTURING PILLAR OR HOLE STRUCTURES IN A LAYER OF A SEMICONDUCTOR DEVICE, AND ASSOCIATED SEMICONDUCTOR STRUCTURE (Inventor)