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Onderzoeker
Arjun Singh
- Disciplines:Nanotechnologie, Sensoren, biosensoren en slimme sensoren, Andere elektrotechniek en elektronica, Ontwerptheorieën en -methoden
Affiliaties
- Elektronische Circuits en Systemen (ECS) (Afdeling)
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Vanaf1 aug 2020 → 30 nov 2018 - Elektrische Energiesystemen en -toepassingen (ELECTA) (Afdeling)
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Vanaf1 aug 2020 → 31 aug 2017 - Afdeling ESAT - ELECTA, Elektrische Energie en Computerarchitecturen (Afdeling)
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Vanaf1 mei 2014 → 31 aug 2017 - Afdeling ESAT - MICAS, Micro-elektronica en Sensoren (Afdeling)
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Vanaf6 jun 2012 → 30 nov 2018 - Duurzame Chemie voor Metalen en Moleculen (Afdeling)
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Vanaf20 jun 2011 → 23 dec 2011
Publicaties
1 - 9 van 9
- Toward sub-20nm pitch Fin patterning and integration with DSA(2016)
Auteurs: Arjun Singh
Pagina's: 97790 - Next generation of decision making software for nanopatterns characterization: application to semiconductor industry(2016)
Auteurs: Arjun Singh
- Manufacturability of dense hole arrays with directed self-assembly using the CHIPS flow(2016)
Auteurs: Arjun Singh
Pagina's: 97770 - Hexagonal hole array patterning for memory applications(2015)
Auteurs: Arjun Singh
Pagina's: 623 - 629 - Patterning sub-25nm half-pitch hexagonal arrays of contact holes with chemo-epitaxial DSA guided by ArFi pre-patterns(2015)
Auteurs: Arjun Singh
Pagina's: 94250 - Impact of sequential infiltration synthesis on pattern fidelity of DSA lines(2015)
Auteurs: Arjun Singh, Ziad El Otell
Pagina's: 94250 - Using chemo-epitaxial directed self-assembly for repair and frequency multiplication of EUVL contact-hole patterns(2014)
Auteurs: Arjun Singh
- Readying directed self-assembly for patterning in semi-conductor manufacturing(2013)
Auteurs: Arjun Singh
Pagina's: 779 - 791 - Development and evaluation of a-SiC:H films using a dimethylsilacyclopentane precursor as a low -k Cu capping layer in advanced interconnects(2013)
Auteurs: Els Van Besien, Cong Wang, Patrick Verdonck, Arjun Singh, Yohan Barbarin, Marc Schaekers, Mikhaïl Baklanov, Sven Van Elshocht
Pagina's: 105 - 107
Patenten
1 - 8 van 8
- Lithographic mask layer (Inventor)
- Metal of ceramic material hardened pattern (Inventor)
- Combined anneal and selective deposition process (Inventor)
- Method for patterning a substrate involving directed self-assembly (Inventor)
- Method for pattern formation on a substrate, associated semiconductor devices, and uses of the method (Inventor)
- Metal or ceramic material hardened pattern (Inventor)
- Method for manufacturing pillar or hole structures in a layer of a semiconductor device, and associated semiconductor structure (Inventor)
- METHOD FOR MANUFACTURING PILLAR OR HOLE STRUCTURES IN A LAYER OF A SEMICONDUCTOR DEVICE, AND ASSOCIATED SEMICONDUCTOR STRUCTURE (Inventor)