A Flexible Radiation Hardened All-Digital PLL/CDR for HEP chipsets
In this project, a radiation hardened All-Digital PLL/Clock-Data Recovery (ADPLL) will be developed. ADPLLs differ from traditional charge-pump PLLs (CPPLL) by implementing the loop filter in the digital domain. They use a digitally controlled oscillator (DCO) instead of a voltage controlled oscillator (VCO). These circuits are highly digital and benefit from recent improvements of digital nanoscale technologies. The goal of this project is the development of an ADPLL core with a wide-range programmable output frequency to support different applications. The ADPLL will be fully protected from single-event upsets with Triple-Modular Redundancy (TMR) in the digital core. Since the analog loop filters are replaced with their digital counterparts, the entire loop can be protected with redundancy. A flexible and programmable loop control is foreseen that can be tuned accordingly to different applications.