A smaller, faster and more energy-efficient complementary STT-MRAM cell uses three transistors and a ground grid: more is actually less

© 1993-2012 IEEE. Spin-transfer torque magnetoresistance random access memory is a major contender for static random access memory replacement in embedded caches at advanced fin field effect transistor nodes. It suffers, however, from the low resistance difference between the bistable states of the magnetic tunnel junction (MTJ). Variability on MTJ resistance and access transistors makes reliable read-out even more challenging. This triggered the use of complementary cells for low level caches needing high performance. This paper, focusing on the lower level caches, shows an improved 3T 2MTJ cell with a ground grid and a novel three transistor read and write operation to improve area density, sense margin, write performance, and write energy consumption. Despite the cell's three transistors, the improved array configuration reduces the cell area by 22% as compared with the 2T 2MTJ cell, making it only 55% larger than a 1T 1MTJ cell. The novel mismatch tolerant read operation uses all three transistors and increases the sense margin by up to 88%. The novel variation resilient write operation also uses all three transistors and takes advantage of the inherent MTJ characteristics and complementary operation of the cell. This increases the write performance by 2times and reduces the write energy by 3times compared with the 2T 2MTJ cell and by 1.5times compared with the 1T 1MTJ cell.

Publication year:2017

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Authors from:Government, Higher Education

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