Radiation hardened high-speed digital circuits with multi-cell upset mitigation techniques for reliable communication links in nanoscale technologies
In this research project, innovative circuit techniques will be developed to enable low power, extremely high-speed radiation hardened digital communication links. Such communication channels are required in complex nuclear facilities such as the Large Hadron Collider, nuclear fusion power plants and high-performance satellites. Generally, digital chips become faster each year with smaller transistors, but they also become more sensitive to high-energy particles coming from nuclear reactions, accelerated beams or cosmic radiation. In the past, such digital systems were protected with triple redundancy. However, due to the shrinking transistor sizes, this is becoming less effective and alternative protection strategies with advanced place methods are required. Radically new digital chip design techniques will be developed to ensure that such digital blocks can be made successfully redundant with advanced algorithms that check whether the geometrical location of millions of digital cells are adequate for surviving the harshest radiation environments. The approach that will be used is based on TCAD simulations (to simulate individual and groups of transistors) and charge sharing between various neighboring cells such that a digital radiationinduced soft-error rate model can be compiled for each multi-million transistor digital netlist. These methods and algorithms will allow to establish radiation hardened digital designs without sacrificing any performance.