Multi-GHz Bandwidth Power-Efficient Nyquist A/D Conversion: Architecture and Circuit Innovations in Deep-Scaled CMOS
The Analog-to-Digital Converter (ADC) is considered the cornerstone of modern electronics due to its fundamental role in virtually any application requiring the transfer of information between the physical (analog) world and the processing (digital) world. This task comes with myriad challenges due to the complex multi-functional ADC nature, further exacerbated when the relevant applications demand stringent performance requirements. Furthermore, bridging the analog and digital worlds fundamentally implies that ADCs must deal with the non-idealities of the former while keeping up with the advancements of the latter.
The rapidly accelerating trend for broader-band signals and software-defined systems has spurred the need for ADCs operating in the multi-GHz sample rate and bandwidth regime. Such converters are highly demanded by applications in the realm of next generation high-speed wireless and wireline communications, automotive radar as well as high-end instrumentation, and have attracted a growing attention from both industries and research institutes. The ever-increasing desire of these systems is to maximize speed, while progressively improving the accuracy and the power efficiency, pushing the performance dimensions to new benchmarks. Meeting these performance requirements at the multi-GHz regime comes with numerous challenges at the circuit, architecture and system levels. On top, the constant technology down-scaling, dictated by the demand for higher functionality at a reduced power and cost, and the improvement in digital performance, exacerbates these challenges for traditional analog-intensive solutions.
This dissertation follows an analytical approach to propose innovative circuit, architecture and system solutions in deep-scaled CMOS and maximize the accuracy·speed÷power of multi-GHz sample rate and bandwidth ADCs. The approach starts by identifying the major error sources of any practical converter's circuits and quantitatively analyzing their significance on the overall performance. This establishes the fundamental accuracy-speed-power limits imposed by circuits and builds an understanding as to what may be achievable from the elementary building blocks in a converter. The analysis is extended to the architectural level by introducing models to estimate and compare the accuracy-speed-power limits of high performance architectures, such as flash, SAR, pipeline and pipelined-SAR. From these models, the SAR comes out as the optimum architecture for a low-to-medium resolution across a wide range of sample rates, while for a medium-to-high resolution, the >2-stage pipelined-SAR hybrid emerges as a promising candidate. To gain insight on the system level and peripheral blocks, a model is introduced to quantitatively compare interleaver architectures, namely direct, de-multiplexing and re-sampling, in terms of achievable bandwidth and sampling accuracy. The strength of the newly introduced models is greatly enhanced by adding technology effects from four deep-scaled CMOS processes; 65nm, 40nm, 28nm and 16nm, building further insight in both the architecture as well as the process choice for optimum performance at given specifications.
To demonstrate the feasibility of the proposed solutions, three multi-GHz prototype ICs are implemented in 28nm CMOS and verified with measurements, while one more is realized in 16nm FinFET CMOS. (1) A 28nm CMOS three-stage triple-latch comparator with a high total gain, a reduced device stacking and parallel direct/feed-forward paths is introduced, which improves altogether the absolute delay, delay slope, and robustness over conventional topologies, while allowing for a similar noise and competitive power compared to the state-of-the-art. (2) A 7-bit single-channel SAR ADC is proposed with a semi-asynchronous processing, a dual-loop bootstrapped input switch, a triple-tail dynamic comparator and a Unit-Switch-Plus-Cap DAC. These features enable a 1.25GS/s sample rate and a >5GHz bandwidth, allowing for a smooth integration into a larger system. The 28nm CMOS prototype ADC compares favorably to the state-of-the-art by achieving among the highest sample rates and the lowest accuracy degradation across the entire band of interest, with an on par overall power dissipation, area and FoM. (3) A 5GS/s 12-bit passive-sampling RF ADC tackles the challenges of wide input bandwidth and high spectral purity in absence of a front-end buffer with a minimized resistance/capacitance network. An on-chip clock conditioning/distribution chain with low jitter ensures sampling purity, while a 3-stage pipelined-SAR hybrid sub-ADC enhances power efficiency. A combined custom analog/synthesized digital calibration improves the spectral performance over the entire band of interest. The 28nm CMOS prototype demonstrates a >6GHz input bandwidth and significantly advances the state-of-the-art among wideband TI RF ADCs. (4) A 16nm FinFET CMOS analog/RF front-end achieves a >30GHz bandwidth, while maintaining an |IMD3|>61dB and a NSD<-157dBFS/Hz. A distributed filter absorbs the ESD capacitance and provides a wideband variable attenuation. The class-AB linearized gain and buffer following the filter, improve altogether the bandwidth, noise and linearity compared to existing state-of-the-art.