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Development of innovative two-terminal selector devices to enable high-density and low-power crosspoint memory arrays

These last years, the demand for high-density and fast-access non-volatile memories has been steadily increasing. However, there is no existing product satisfying this need today, between the fast but volatile DRAM technology and the high-density but slow-access 3D Flash technology. Hence, the ‘Storage Class Memory’ (SCM) has emerged to fill this speed-density gap in the memory hierarchy, enabling the development of future computing and/or storage systems by providing a fast and cheap memory alternative. Several emerging memory concepts, like Resistive Random-Access Memory (RRAM), Phase-Change RAM (PCRAM), or Magnetic RAM (MRAM) concepts hold the promise of showing both speed and density specifications of SCM. On the other hand, in today’s memory array cross-point architecture, the main factor limiting high-density integration is the “sneak path” current or capacitive issue during read and write programming of the memory device. To overcome this issue a two-terminal access device (selector) in series with the memory element is required to enable addressing individual memory cells in an array without disturbing the others. This select device must be scalable, have high rectification ability, following the operation mode of the memory cell (typically bipolar) and allow for high drive current densities, required to switch the memory element. To fulfill these requirements, many selector concepts are currently under investigation. Among others, there is the chalcogenide-based Ovonic Threshold Switch (OTS) technology. For high enough voltages, OTS technology relies on the appearance of a negative differential resistance (NDR) branch in the selector I-V characteristic to grand high driving capability and large non-linearity. These performances come at the expense of relatively high voltage and voltage spiking across the memory element. Although excellent potential was demonstrated for this technology, the switch mechanism is not well understood. Alternative selector concept, generally based on the rectifying behavior of Schottky contact are also investigated in view of close integration with MRAM technology. Indeed, such selectors, characterized by a diode-like behavior, generally avoid OTS voltage issue which is critical for a low voltage, low power technology such as MRAM. In addition to these two technologies, the scope of this PhD will also include a broad research activity on the topic exploring Mixed Ionic Electronic Conductors (MIEC), Metal-Semiconductor-Metal diode, novel vertical IGZO-based diode etc. The purpose of this PhD is to investigate thoroughly the electrical performances and reliability properties of the above-mentioned selector devices by studying the roles of composition, material variations, and integration processes, in order to identify knobs for device improvement. In addition, a large part of the PhD work will be to develop a physics-based switching model, which should help complement compact, parametric models used at circuit simulation level, in order to enable assessment of the array performance. Overall, an important output of the PhD will be to establish the intrinsic limitations and potentials of the technology.

Date:23 Oct 2019 →  Today
Keywords:Storage Class Memory, Selector device, Cross-point memory array, Semiconductor memory
Disciplines:Semiconductor devices, nanoelectronics and technology, Memory components, Nanoelectronics
Project type:PhD project