Secure Hardware for Post-Quantum Cryptography

New cryptographic standards, secure against quantum computers, were developed to replace the current public key algorithms (RSA & ECC) that are not secure against the quantum threat. Efficient and secure hardware implementations (FPGA & ASIC) of these standards are an essential aspect for their rollout in real-world applications. However, the computational complexity and excessive data sizes make the design of efficient co-processors or instruction set extensions a challenge. The goal of this PhD thesis is to develop, design and implement new techniques, strategies and architectures for securely and efficiently implementing these novel schemes in hardware. The main focus of this work is implementations on embedded devices, where the area, power or/and energy budget is limited and where protection against physical attacks (e.g. side-channel and fault attacks) needs to be incorporated.