Area selective deposition, a bottom-up approach for the fabrication of nano-electronic devices

During the last decades, an enormous increase in applications has occurred in the field of
information, telecommunication and life sciences. To sustain this growth, the amount of integratedcircuits (IC) in our daily life is increasing, ranging from computers, tablets, mobile phones, TV’s to
cars, smart glasses and healthcare. Innovations in electronics do not only increase computing power
and memory, but also make our devices more energy-efficient by reducing the power consumption.
Such innovations are enabled by miniaturization of device dimensions, new materials with
improved properties, and new device architectures and concepts, often implying an evolution
towards three dimensional (3D) structures. This evolution brings many challenges to the
(photo)chemical and physical techniques involved in the manufacturing of nano-electronic devices.
As the device dimensions decrease, the combination of the conventional top-down patterning
techniques, such as photolithography, with alternative bottom-up strategies becomes more and
more attractive. Examples of bottom-up approaches include self-aligned multiple patterning,
directed self-assembly (DSA) and area-selective deposition (ASD).
In ASD, a material is deposited only according to a predefined pattern (growth pattern),
while the rest of the surface (non-growth pattern) remains unaffected because growth is
inhibited. ASD can be achieved by surface chemistry dependent deposition processes like
chemical vapor deposition (CVD) and atomic layer deposition (ALD). In ALD, a thin film is deposited
on a substrate by self-limiting surface reactions of gas phase precursors. ALD is therefore sensitive
to the substrate surface, which can be chemically modified to enable or prevent growth. ASD has
been achieved through surface passivation by self-assembled monolayers. However, these
monolayers are not always thermodynamically stable at the conditions of the deposition process,
resulting in loss of selectivity. In addition, a fundamental question is how the process of selfassembly
behaves on substrates with 3D topography and in patterns with nm-scale dimensions.

The approach for ASD investigated here, relies on inherent differences in surface reactivity, which
is scalable and compatible with 3D topographies. ASD is of great interest for nano-electronic device
manufacturing as it can enable self-aligned deposition, bottom-up fill of 3D structures and pattern
tone inversion. In addition, it can significantly simplify integration flows because it
eliminates patterning steps. As such, ASD will not only reduce cost but also the ecological footprint
of nano-electronic device manufacturing.
However, industrial applications of ASD are currently limited to selective epitaxial growth
(SEG) of semiconductors and metal capping layers on interconnect structures, mainly because up
till now ASD has been studied only for a limited number of processes and materials. In addition,the inherent surface dependence of ALD and CVD is rarely sufficient, as inhibited growth is often
associated by island or nanoparticle formation. Undesired nanoparticle formation on the nongrowth
pattern is one of the greatest challenges of ASD, and is currently impeding the widespread
use of ASD in nano-electronic device fabrication. Defect mitigation strategies based on
nanoparticle diffusion or etch need to be developed, which requires insight into the nucleation
mechanism. Therefore, the understanding of the underlying fundamental processes relating to
nucleation and growth is essential for the sustained growth of the ASD field.