Secure and efficient implementation of Software Masking on CPUs

Masking is a typical approach of protecting a cryptographic implementation against power analysis which relies on certain assumptions. However, recent observations show that the security of such a software countermeasure in a practical application can be reduced due to micro-architectural features and side-effects. This work aims to understand better the leakage sources and CPUs design aspects that reduce the protection of software masked implementation. Our study will first concentrate on the core components of the open source RISC-V processor.