A 40nm bulk CMOS line driver for broadband communication

A 40nm CMOS line driver operating from a 5.4V supply is presented. The driver can output a 7.7V peak to peak output signal in a 50Ω load. For high supply voltage compliance, transistor stacking and dynamic bias is being used. A line driver prototype PCB is assembled and characterized. A gain up to 19dB is measured over a 730MHz bandwidth. A OP1dB of 14dBm & PSAT of 21.7dBm is measured in 50Ω. During OFDM tests with a 15dB PAPR signal, a peak SNDR of 41dB is measured.

ISBN:9781509029723

Publication year:2016

BOF-keylabel:yes

IOF-keylabel:yes

Authors from:Higher Education

Accessibility:Closed