System Architecture exploration for AI accelerator platforms

During this PhD you will build architecture models for neural network accelerators and study the mapping of a variety of algorithms on them, to co-optimize architecture, algorithms and eventually circuit design for AI accelerators. The goal is to explore a multitude of architectures: systolic array based, analog/mixed signal and even in-memory compute based will be considered. You will work with that design analog-in-memory compute solutions based on emerging memory technology like MRAM or RRAM but your scope will be wider than just that, to look at a full, programmable accelerator that will need a heterogeneous mix of CPU, digital accelerator logic, next to, possibly, in-memory compute fabrics. The goal is to find the right choices to deal with memory pressure, compute requirements, power efficiency and flexibility. Building the right modelling tools will be an important part of the work, as this will allow for fast and efficient exploration of the design space, and possibly automated network and hardware architecture search based solutions.