Performance and Resource Modeling for FPGAs using High-Level Synthesis tools

High-performance computing with FPGAs is gaining momentum with
the advent of sophisticated High-Level Synthesis (HLS) tools. The performance of
a design is impacted by the input-output bandwidth, the code optimizations and
the resource consumption, making the performance estimation a challenge. This
paper proposes a performance model which extends the roofline model to take into
account the resource consumption and the parameters used in the HLS tools. A
strategy is developed which maximizes the performance and the resource utilization
within the area of the FPGA. The model is used to optimize the design exploration
of a class of window-based image processing application.

ISBN:978-1-61499-380-3

Keywords:Roofline Model, High-Level Synthesis, FPGA