Dynamic Power Management in Heterogeneous Multi-Core Processors

Heterogeneous processors (e.g., ARM’s big.LITTLE) provide flexibility in power-constrained environments by executing applications on the ‘big’ high-performance core when there is available power budget and on the ‘little’ core when power is limited. This project explores dynamic power management in heterogeneous chip-multiprocessors (HCMPs) with per-core DVFS, optimizing performance within a power limit per thermally significant time period. We decompose the overall problem statement into three sub-problems: (i) power budget partitioning; (ii) criticality-aware power allocation; and (iii) identification of the optimal operating point (core type, frequency setting, SMT concurrency level) per thread.