Design of radiation tolerant timing systems with sub-picosecond accuracy.

The goal of this research was to develop and test integrated CMOS circuits for radiation tolerant time-based circuits with picosecond accuracy for nuclear applications and high-energy physics. The main applications for which these circuits were developed, are time-based readout interfaces in high-energy physics particle detectors, clock generation and data-transmission for these detectors. During this research, a radiation tolerant Time-to-Digital Converter (TDC) and a low noise clock synthesizer were designed and optimized for the particle detectors at CERN. 

A short overview on the radiation effects and mitigation techniques to ionizing radiation is given, together with a discussion on the practical aspects which are required in modern TDCs and frequency synthesizers.

A high-resolution TDC is presented with a discussion on the design aspects and the practical implementations of the circuit which are required in nuclear environments. The TDC is based on a Delay-Locked Loop (DLL) that has two phase detection circuits to boost the recovery time after an energetic particle disturbs the circuit. The functionality of the DLL ensures that the timing resolution of the TDC remains the same after irradiation. Furthermore, this DLL has a new phase detector architecture which reduces static-phase offsets in the phase detectors through a correlated sampling mechanism which has been implemented for the first time in the time domain. The circuit was prototyped in a 40 nm CMOS technology and a 4.8 ps resolution was measured with a 4.2 mW power consumption.

DLL based TDCs or serial communication links do require a low-noise, high-frequency reference clock. For a 64 channel TDC, a 2.56 GHz frequency synthesizer was designed to upconvert the 40 MHz reference clock of the Large Hadron Collider (LHC) at CERN to a 2.56 GHz high speed clock with a targeted rms jitter below 1 ps. A radiation hardened Phase Locked Loop was designed in which both an LC-tank oscillator and ring oscillator were present. The chip was prototyped in a 65 nm COS technology. These circuits were, in a next step, irradiated to make a comparison between ring and LC-tank oscillators in terms of noise, radiation damage and single-event effects. The devices were irradiated with X-rays up to 600 Mrad to study the Total Ionizing Dose effects on the circuits and were also irradiated with heavy-ions to study the single-event effects on the oscillators.  The clock generator has a power consumption of 11.7 mW and had an integrated rms jitter of only 345 fs. Triple Modular Redundancy was used in the digital circuits to protect them from soft errors. A new phase detector architecture is presented which minimizes the error rate due to high-energy particles in frequency synthesizers. The devices were also tested for temperature variations from -25 °C up to 125 °C.

From the results gathered in the radiation experiments, an improved LC-tank oscillator was designed which has a reduction of the sensitivity to single-event upsets of more than 600 times compared to a traditional implementation which is mainly due to the cross section of the tuning varactor of the oscillator. This technique was also experimentally verified.