Multiport SRAM in sequential 3D technology Interuniversitair Micro-Electronica Centrum vzw
A multiport memory cell (60) for register files is disclosed. Vertically stacked top and bottom tier of the memory cell are electrically interconnected through a pair of vias (V1, V2) and comprise each an active device layer and a metal layer stack. The memory cell is partitioned to have a latching circuit (T1-T4) and at least one write port (WP) located in the bottom tier and at least two read ports (RP1, RP2) in the top tier. A word line trace (62) for controlling the at least one write port is formed in the bottom tier metal layer stack and comprises two terminal sections (62a, 62b) and ...