Layout Optimizations for THz Integrated Circuit Design in Bulk Nanometer CMOS KU Leuven
© 2017 IEEE. Scaling in CMOS has increased the attainable operational frequencies, while greatly increasing the transistor's parasitic modeling complexity. Additionally, the performance of the ever-smaller on-chip passives for mm-wave and THz circuits is being degraded by numerous process requirements and limitations, such as high densities of dummy metals. This work discusses the main transistor layout trade-offs for high-frequency performance ...