A COUNTER ARCHITECTURE FOR ONLINE DVFS PROFITABILITY ESTIMATION Universiteit Gent
This invention describes a hardware counter architecture to accurately estimate the profitability of Dynamic Voltage and Frequency Scaling (DVFS) in a processor. The counter architecture estimates what the impact is of scaling clock frequency and supply voltage on performance and energy consumption. The total execution time of a program running on a processor can be divided into a pipelined fraction subject to clock frequency and a non-pipelined fraction due to off-chip memory accesses. The counter architecture estimates these two fractions, from which DVFS profitability can be estimated: the ...