Bit cell with isolating wall. Interuniversitair Micro-Electronica Centrum vzw
A bit cell (10) for a Static Random-Access Memory, SRAM, is provided, comprising a first and second pair of complementary transistors as well as a first pass-gate transistor (PG1) and a second pass-gate transistor (PG2). A first inverter gate electrode (121) forms a common gate electrode for the first pair of complementary transistors and a second inverter gate electrode (122) forms a common gate electrode for the second pair of complementary transistors. Further, a first pass gate electrode (131) forms a gate of the first pass-gate transistor and a second pass gate electrode (132) forms a ...