Titel Deelnemers "Korte inhoud" "Ultra Low Power Detection Circuits in 130nm CMOS for a Wireless UWB Localization System" "Christophe De Roover, Michiel Steyaert" "This paper presents two detection circuits with an ultra low power consumption in the nW-range. A voltage detection circuit is designed and measured of which the output switches if the supply voltage reaches 1V. It consumes an average current of merely 3nA. Also a power dip detection circuit is designed and measured which detects if an RF-signal is present at the input. The minimal needed input power is −24.5dBm, and it operates from a supply voltage of 0.5V up to 1V and consumes only 5nW to 65nW respectively when active. It operates with a carrier frequency from 40MHz up to 900MHz. It can serve as an OOK-demodulator for bitrates up to 6.67kbps. The die area of both circuits combined, excluding buffers and including decoupling capacitors, is 310μm×550μm." "A Low Power Dynamic Circuit Topology towards a-IGZO Thin-Film Ultrasonic Transducer Driving Circuit" "Jonas Pelgrims, Kris Myny, Wim Dehaene" "A 4bit counter with dynamic logic is demonstrated running up to 3.5MHz at 8.4V using amorphous indium-gallium-zinc-oxide thin-film transistors (a-IGZO TFT). Dynamic logic is selected to achieve the required speed for digital circuits driving ultrasonic transducers enabling large-area ultrasonic applications. In addition a back-gate switching technique is introduced in order to further reduce logic area and increase speed of the dynamic gate, illustrating to our knowledge the best in class EDP product for a small footprint meeting the requirements for ultrasonic transducer driving." "CMOS Circuitry for Low Power Ring-based Silicon Photonics Optical Link" "Michal Rakowski" "In the near future, Tb/s-class aggregate bandwidth input/output (I/O) circuits will be needed for high-end performance computing systems. A high-performance I/O using optical transmission technology is being considered to overcome the limitation of a conventional electrical I/O in terms of data rate per channel, a bandwidth per millimeter and power consumption. A silicon photonics technology is very promising candidate to realized Tb/s-class aggregate I/O bandwidth with improved energy efficiency targeting cost-effective short-range optical links. The main focus in this work is put on CMOS circuitry design to enable low power and high speed optical link between two packages. On the transmitter side of the optical link, energy efficient CMOS driver circuit was co-designed with silicon ring modulator to maximize optical modulation amplitude and to reduce insertion loss. The receiver circuit, designed as a chain of inverted-based stages allows to amplify and convert current pluses detected by a germanium photodiode to usable voltage. The models of the key silicon photonics devices: ring modulator and germanium photodiode allowed to improve the CMOS circuit design targeting the highest energy efficiency. The models of the optical active devices as well as grating couplers, silicon waveguide and fibers were implemented in Verilog-A allowing co-simulation with the CMOS circuits. Thanks to that the complete CMOS silicon photonics link was simulated in a single environment. To demonstrate optical transmission silicon photonics die was integrated with co designed CMOS chip by a standard flip-chip technique. The silicon photonics chip containing optical active and passive devices was fabricated in imecs 200mm pilot line using a subset of 130nm CMOS processing modules. The demonstrator allow to transmit and received data via optical link at 10Gb/s and 20Gb/s. Measured power consumption on the complete optical transceiver showed very good agreement when compared with the simulations results." "Ultra low power litho friendly local assist circuitry for variability resilient 8T SRAM" "Wim Dehaene" "This paper presents litho friendly circuit techniques for variability resilient low power 8T SRAM. The new local assist circuitry achieves a state-of-the-art low energy and variability resilient WRITE operation and improves the degraded access speed of SRAM cells at low voltages. Differential VSS bias increases the variability resilience. The physical regularity in the layout of local assist circuitry enables litho optimization thereby reducing the area overhead associated with existing local assist techniques. Statistical simulations in 40nm LP CMOS technology reveals 10x reduction in WRITE energy consumption, 103x reduction in write failures, 6.5x improvement in read access time and 31% reduction in the area overhead. © 2012 EDAA." "A low power, multi-rate clock-and-data recovery circuit and MAC preprocessor for 40 Gbit/s cascaded bit-interleaving passive optical networks" "Arno Vyncke" "Implementation of Bus Bar Switching and Short Circuit Constraints in Optimal Power Flow Problems" "Tom Van Acker, Dirk Van Hertem" "The topology of an electric network heavily influences power system operations, power flows, short circuit currents and certain reliability aspects. While meshing increases reliability, it also increases the short circuit power, which can bea problem especially in highly meshed grids. Bus bar switchingis often employed by the system operator for preventive andcorrective actions, as it is a quasi-free control action. Theintroduction of binary variables, representative of the state ofthe circuit breakers, in the optimization description allows for bus bar switching resulting in the adaptation of the topologyof a grid. The goal of this paper is to present an algorithmthat is able to propose a topology that complies with the ShortCircuit Constraints (SCC) whilst respecting the Power FlowConstraints (PFC). Both are adapted in such a way that they allow binary switching actions. The mathematical descriptionof the optimization problem is a Mixed Integer Non Convex Quadratic Constraint Program (MINCQCP) and is implemented in AMPL using the Couenne solver. The paper concludes with two tests that show the functionality of the approach." "A comparison between minimized extracorporeal circuits and conventional extracorporeal circuits in patients undergoing aortic valve surgery: is 'minimally invasive extracorporeal circulation' just low prime or closed loop perfusion ?" "Pascal Starinieri, Peter E. Declercq, Boris ROBIC, Alaaddin Yilmaz, Michiel Van Tornout, Jasperina Dubois, Urbain Mees, Marc HENDRIKX" "Introduction: Even though results have been encouraging, an unequivocal conclusion on the beneficial effect of minimally invasive extracorporeal circulation (MiECC) in patients undergoing aortic valve surgery cannot be derived from previous publications. Long-term outcomes are rarely reported and a significant decrease in operative mortality has not been shown. Most studies have a limited number of patients and are underpowered. They merely report on short-term results of a heterogeneous intraoperative group using different types of ECC system in aortic valve surgery. The aim of the present study was to determine whether MiECC systems are more beneficial than conventional extracorporeal systems (CECC) with regard to mortality, hospital stay and inflammation and with only haemodilution and blood-air interface as differences. Methods: We retrospectively analysed data regarding mortality, hospital stay and inflammation in patients undergoing isolated aortic valve surgery. Forty patients were divided into two groups based on the type of extracorporeal system used; conventional (n=20) or MiECC (n=20). Results: Perioperative blood product requirements were significantly lower in the MiECC group (MiECC: 0.20.5 units vs CECC: 0.9 +/- 1.2 units, p=0.004). No differences were seen postoperatively regarding mortality (5% vs 5%, p=0.99), total length of hospital stay (10.6 +/- 7.2 days (MiECC) vs 12.1 +/- 5.9 days (CECC), p=0.39) or inflammation markers (CRP: MiECC: 7.09 +/- 13.62 mg/L vs CECC: 3.4 +/- 3.2 mg/L, p=0.89). Conclusion: MiECC provides circulatory support that is equally safe and feasible as conventional extracorporeal circuits. No differences in mortality, hospital stay or inflammation markers were observed." "Power Management Circuits for Low-Power RF Energy Harvesters" "Michele Caselli" "A low power mm-wave oscillator using power matching techniques" "Lianming Li, Patrick Reynaert, Michiel Steyaert" "A low power low voltage 90nm CMOS mm-wave oscillator using a power matching technique is presented. The oscillator uses an inductive divider to create impedance matching for the amplifier. With this technique, the effect of the varactor loss on the phase noise is reduced and the oscillator power efficiency is increased. The proposed oscillator achieves a phase noise of -95dBc/Hz at 1MHz offset from 64GHz carrier, consuming 3.16 mW from a 0.6 V supply voltage. The figures-of-merit are FOM -186 and FOMT -185 respectively. The tuning range is from 61.1 GHz to 66.7 GHz and the measured output power is about -14 dBm. © 2009 IEEE." "W-band differential power amplifier design in 45 nm low power CMOS" "Noël Deferm, Patrick Reynaert" "In this paper, a comparison is made between two 94 GHz differential CMOS power amplifiers. Both a cascode and common source PA are designed and measured. They both show that excellent mm-wave performance can be achieved in a nanometer scale CMOS technology. Design and performance trade-offs between both topologies are discussed. Efficiency, reliability, linearity and stability are key parameters in this discussion. The PA's were designed in a 45 nm low power CMOS process. Low loss transformers with excellent inter-stage common mode rejection are utilized to implement the matching networks. © 2013 Elsevier Ltd. All rights reserved."