Titel Deelnemers "Trapping of Hot Carriers in the Forksheet FET Wall: A TCAD Study" "Michiel Vandemaele, Guido Groeseneken" "ESD nMOSFETs in Advanced Bulk FinFET Technology With Dual S/D Epitaxy" "Wen-Chieh Chen, Guido Groeseneken" "LaSiOx- and Al2O3-Inserted Low-Temperature Gate-Stacks for Improved BTI Reliability in 3-D Sequential Integration" "Zhicheng Wu, Guido Groeseneken" "Investigation of the Impact of Hot-Carrier-Induced Interface State Generation on Carrier Mobility in nMOSFET" "Zhicheng Wu, Guido Groeseneken" "Modeling and Calibration of Device Non-Idealities in Steep-Slope Devices" "Jasper Bizindavyi" "Technological innovations, such as the personal computer and the smartphone, have transformed our society into the modern Digital Age within a short period of time. These innovations have been made possible by consistently scaling down the metal-oxide-semiconductor field-effect transistor (MOSFET) and the supply voltage of integrated circuits. Today, however, the thermionic lower limit of the subthreshold swing (SS) of MOSFETs prevents any further reduction in the supply voltage. As a result, conventional MOSFET scaling is steadily approaching its end.Steep-slope devices are a class of novel transistor technologies that are characterized by a low SS and enable further reductions in the supply voltage. The most intensively studied steep-slope device is the tunnel field-effect transistor (TFET). At its core, the TFET is a gated reverse-biased Esaki diode that utilizes quantum-mechanical band-to-band tunneling (BTBT) to obtain a subthermionic SS. A second, somewhat more controversial device is the steep-slope ferroelectric field-effect transistor (SS-FeFET). The SS-FeFET is essentially a conventional MOSFET with a ferroelectric material incorporated into the gate stack that exploits the coherent switching of the polarization in the ferroelectric layer to obtain a sub-thermionic SS.Despite a decade of major research efforts, there still remains a significant discrepancy between the theoretically predicted and the experimentally observed performance of the TFET and the SS-FeFET. As a consequence, it has become increasingly more clear that it is important to also include the impact of device non-idealities in the performance predictions. In this thesis, we therefore theoretically investigate, model, and/or calibrate several critical device non-idealities in TFETs and SS-FeFETs.In the first and main part of this thesis, we begin with an investigation of the variation in temperature dependence of the BTBT current between different Esaki diode and TFET structures, as it is not well understood. In the case of conventional Esaki diodes, we find that the BTBT current is quasi-temperature-independent, which is in agreement with the observations in literature. However, in contrast to what is commonly assumed, we demonstrate that this observation cannot be generalized to TFETs and unconventional Esaki diodes, as the BTBT current becomes significantly more temperature dependent.We then proceed by investigating the impact of band-tails tunneling (BTT), which arises in TFETs and Esaki diodes due to the very high doping concentrations. We develop a semi-classical model for ballistic BTT by assuming a phenomenological band structure model for the band-tails states and utilizing the Tsu-Esaki expression for ballistic transport. Our ballistic BTT current model is then calibrated using the measured current-voltage characteristics of multiple highly-doped III-V Esaki diodes. This enables us to demonstrate that the discrepancy between the theoretically predicted and the experimentally observed performance of Esaki diodes can be resolved by accounting for high-doping-induced BTT.Next, we utilize our calibrated BTT current model to identify the main signatures of BTT in TFETs. Our examination reveals that it is only possible to distinguish between a TFET with a dominant BTT current and a TFET with a dominant trap-assisted-tunneling current by analyzing the output characteristics. Lastly, we use our calibrated model to assess the predicted impact of BTT on the device performance and SS of TFETs and find it to be limited. As a consequence, we conclude that the TFET is predicted to retain its advantage over the MOSFET at low supply voltages even in the presence of BTT.In the second part of this thesis, we examine the thermodynamic equilibrium framework of ferroelectric heterostructure systems, such as the SS-FeFET. We formally establish that the Grand Potential is the appropriate thermodynamic potential to analyze the equilibrium states of free-charge conducting ferroelectric systems at constant applied voltage. We furthermore show that the Gibbs free energy only becomes the appropriate thermodynamic potential in the limiting case of perfectly non-conductive systems. Lastly, we demonstrate that any free-charge accumulation in the system tends to destabilize the polarization switching in the ferroelectric." "Modeling of Repeated FET Hot-Carrier Stress and Anneal Cycles Using Si-H Bond Dissociation/Passivation Energy Distributions" "Michiel Vandemaele, Guido Groeseneken" "Impact of ambient temperature on the switching of voltage-controlled perpendicular magnetic tunnel junction" "Jan Van Houdt, Guido Groeseneken" "GaN power IC design using the MIT virtual source GaNFET compact model with gate leakage and VT instability effect" "Guido Groeseneken" "Effects of Back-Gate Bias on the Mobility and Reliability of Junction-Less FDSOI Transistors for 3-D Sequential Integration" "Zhicheng Wu, Guido Groeseneken" "Compact Modeling of Multi-Domain Ferroelectric FETs: Charge Trapping, Channel Percolation and Nucleation-Growth Domain Dynamics" "Yang Xiang, Md Nur Kutubul Alam, Guido Groeseneken, Jan Van Houdt"