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A Systematic M safe-error Detection in Hardware Implementations of Cryptographic Algorithms

Boekbijdrage - Boekhoofdstuk Conferentiebijdrage

This paper presents a procedure that checks whether a hardware implementation of a cryptographic algorithm is vulnerable to M safe-error attacks. It takes a registertransfer level (RTL) description of a design as an input and exposes the exact timing and a memory element that is a possible target of the attack. As a proof of concept, the presented procedure is applied to a hardware implementation of the Montgomery Powering Ladder, an exponentiation algorithm commonly used in public-key cryptography. © 2012 IEEE.
Boek: 5th IEEE International Workshop on Hardware-Oriented Security and Trust - HOST 2012
Pagina's: 96 - 101
ISBN:9781467323390
Jaar van publicatie:2012