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Measurements of an EMC test chip for lower EME in CMOS digital ICs
Boekbijdrage - Boekhoofdstuk Conferentiebijdrage
In digital designs, it becomes more and more important to reduce the supply current variations (di/dt noise) they induce in the supply lines. This is due to the fact that steep variations in supply current give rise to EM (Electro-Magnetic) emission. Hence, integrated circuits with lower emission are greatly demanded, especially in the automotive market. This paper describes several efficient low EME design techniques. Based on a 0.35 μm CMOS EMC test chip, the effectiveness of emission reduction techniques is quantified through a set of measurements. © 2008 IEEE.
Boek: EMC Europe, International Symposia on EMC
Pagina's: 543 - 548
Authors from:Higher Education