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A 1.25-GS/s 7-b SAR ADC With 36.4-dB SNDR at 5 GHz Using Switch-Bootstrapping, USPC DAC and Triple-Tail Comparator in 28-nm CMOS

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© 2018 IEEE. This paper presents a 1.25-GS/s 7-b single-channel successive approximation register (SAR) analog-to-digital converter (ADC) that achieves a low input frequency SNDR/SFDR of 41.4/51 dB, while the SNDR/SFDR at Nyquist is 40.1/52 dB and remains still 36.4/50.1 dB at a 5-GHz input frequency (eighth Nyquist zone) without any calibration. The high and nearly constant linearity is enabled by an improved bootstrap circuit for the input switch, while the high sampling rate, the highest among recently published >34-dB SNDR single-channel SAR ADCs, is accomplished by a triple-tail dynamic comparator and a unit-switch-plus-cap (USPC) capacitive digital-to-analog converter (CDAC). To further enhance the ADC speed, the SAR logic operates in parallel to the comparator, eliminating its timing from the critical loop. The prototype chip in 28-nm bulk CMOS occupies a core area of 0.0071 mm2and consumes 3.56 mW from a 1-V supply, leading to a Walden figure-of-merit of 34.4 fJ/conversion-step at Nyquist.
Tijdschrift: IEEE Journal of Solid-State Circuits
ISSN: 0018-9200
Issue: 7
Volume: 53
Pagina's: 1889 - 1901
Aantal pagina's: 13
Jaar van publicatie:2018
Trefwoorden:Elektronica en elektrotechniek