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Octrooi

Method for producing an integrated circuit including a metallization layer comprising low k dielectric material

According to the invention, a metallization layer of an IC is produced, having a lower via level and an upper trench level. To this aim, dual damascene processing is applied on a stack of two layers : the bottom layer (1') being a layer comprising a porous low-k dielectric wherein the pores have been filled by a template material and the top layer being a template layer (3'). This stack is obtained by depositing a template layer (3) on top of a porous low-k dielectric and annealing the obtained layer stack in order to let the template material diffuse into the pores of the low-k layer. At the end of the anneal process, a stack of a pore-filled layer (1') and a template layer (3') is obtained. Vias (14) are etched in the low-k layer (1') and trenches (15) are etched in the template layer (3'). The template pore-filling protects the low-k dielectric during plasma etching, metal barrier deposition and metal deposition.
Octrooi-publicatienummer: EP3236494
Jaar aanvraag: 2018
Jaar toekenning: 2018
Jaar van publicatie: 2018
Status: Toegewezen
Technologiedomeinen: Semiconductoren
Gevalideerd voor IOF-sleutel: Ja
Toegewezen aan: Associatie KULeuven