Onderzoeker
Nereo Markulic
- Trefwoorden:Elektronica en elektrotechniek
Affiliaties
- Elektronica en Informatica (Departement)
Lid
Vanaf1 dec 2023 → Heden - Faculteit Ingenieurswetenschappen (Faculteit)
Lid
Vanaf25 sep 2015 → 11 jun 2018 - Elektronica en Informatica (Departement)
Lid
Vanaf1 okt 2012 → 31 dec 2017
Publicaties
1 - 9 van 9
- Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation(2021)Series: 2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
Auteurs: Pratap Tumkur Renukaswamy ., Nereo Markulic, Piet Wambacq, Jan Craninckx
Pagina's: 1-5 - A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/μs Slope and 1.2-GHz Chirp-Bandwidth(2020)
Auteurs: Pratap Tumkur Renukaswamy ., Nereo Markulic, Piet Wambacq, Jan Craninckx
Pagina's: 3294-3307 - A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/μs Slope and 1.2GHz Chirp Bandwidth(2020)
Auteurs: Nereo Markulic, Qixian Shi, Jan Craninckx
Pagina's: 278-280Aantal pagina's: 3 - A 5.5-GHz Background-Calibrated Subsampling Polar Transmitter With-41.3-dB EVM at 1024 QAM in 28-nm CMOS(2019)
Auteurs: Nereo Markulic, Pratap Tumkur Renukaswamy ., Ewout Martens, Barend van Liempd, Piet Wambacq, Jan Craninckx
Pagina's: 1059-1073 - A 5.5 GHz Background-Calibrated Subsampling Polar Transmitter with −41.3 DB EVM at 1024 OAM in 28NM CMOS(2018)
Auteurs: Nereo Markulic, Ewout Martens, Barend van Liempd, Jan Craninckx
Pagina's: 215-216Aantal pagina's: 2 - A Fractional-n subsampling PLL based on a digital-to-time converter(2016)
Auteurs: Nereo Markulic, Kuba Raczkowski, Piet Wambacq, Jan Craninckx
Pagina's: 66-71 - A self-calibrated 10Mb/s phase modulator with -37.4dB EVM based on a 10.1-to-12.4GHz, -246.6dB-FOM, fractional-N subsampling PLL(2016)
Auteurs: Nereo Markulic, Kuba Raczkowski, Ewout Martens, Pedro Emiliano Paro Filho, Benjamin Hershberg, Jan Craninckx
Pagina's: 176-177Aantal pagina's: 2 - A 10-bit, 550-fs step Digital-to-Time Converter in 28nm CMOS(2014)
Auteurs: Nereo Markulic, Kuba Raczkowski, Jan Craninckx
Pagina's: 79-82Aantal pagina's: 4 - A 9.2–12.7 GHz wideband fractional-N subsampling PLL in 28nm CMOS with 280fs RMS jitter(2014)
Auteurs: Kuba Raczkowski, Nereo Markulic, Benjamin Hershberg, Joris Van Driessche, Jan Craninckx
Pagina's: 89-92Aantal pagina's: 4
Patenten
1 - 4 van 4
- Dtc-based pll and method for operating the dtc-based pll (Inventor)
- Polar transmitter and method for generating a transmit signal using a polar transmitter (Inventor)
- Polar transmitter and method for generating a transmit signal using a polar transmitter
- DTC-based PLL and method for operating the DTC-based PLL