Analysis of the Impact of Mechanical Stress on Three-Dimensional Memory Devices

To increase the performance of memory cells in silicon technology without increasing their size on the chip, the third dimension is used. This is done by stacking many thin oxide and nitride layers alternating on top of each other, etching holes in them, etching part of the layers away, filling them with metals, oxides etc. This complex, multiple stack of layers raises large concerns about mechanical stresses. First of all, the layer stack induces global stresses, resulting in a curvature of the silicon wafers, which in turn has impact on the accuracy of lithography and etch steps. Secondly, the patterning of those layers decrease the residual stress and deform the remaining structures which may induce mechanical instability such as buckling. The etching and filling of holes and tunnels in the layers and filling them with different materials also induces local stresses which might result in defects, delamination or even fracture. A third concern is the effect of this stress on the functioning of the memory device itself. And a last concern is whether this stress might impact other devices which are located in the silicon near the memory device. The roadmap of these 3D memory cells foresees to increase the number of layers, even stacking multiple cells. The goal of this PhD is to understand the fundamentals of the processing induced stress in 3D memory cells, its impact on devices and periphery, and an extrapolation to the end of the roadmap. To study these problems, the PhD student will in a first phase perform experiments to obtain information on the mechanical properties of all the materials used in this process. These properties will next be used to build finite element models which can predict the global and local stresses, and the impact of processing variations (example film thickness, number of layers, etc.) on the stress. The models have to be verified by comparison with experiments. In a second phase, experiments will be performed to study the sensitivity of the memory devices to stress and the possible impact on nearby transistors. This requires to perform electrical measurements on the memory devices and on the transistors while applying external stress. Also this information has to be included in a model, to allow prediction of this impact and optimization of the full 3D-memory device flow. In a last phase, the impact of stress on the roadmap for these devices will be assessed. Questions to be addressed are: Is stress limiting the future 3D extension of these memory cells, what are the limitations, are there possible solutions or alternatives, are there new concerns to be expected?

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