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A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/μs Slope and 1.2GHz Chirp Bandwidth

Boekbijdrage - Boekhoofdstuk Conferentiebijdrage

A 10GHz FMCW subsampling PLL is presented, that uses a low-power charge-integrating QDAC to tune the VCO for wideband low-noise modulation. Nonlinearities in the QDAC modulation path are corrected within 700µsec cold start-up, followed by a full on-chip background calibration engine to track supply and temperature variations. The PLL consumes 11.7mW (of which <0.5mW in the QDAC) to generate a 23.6MHz/µs chirp slope with 89kHz rms-frequency-error for 1.21GHz chirp-bandwidth.
Boek: 2020 International Solid-State Circuits Conference
Pagina's: 278-280
Aantal pagina's: 3
Jaar van publicatie:2020
Trefwoorden:PLL, FMCW radar, Sub-sampling PLL, Integrating DAC, Background calibration
Toegankelijkheid:Closed