Characterization and Modeling of Hot Carrier Degradation in N-Channel Gate-All-Around Nanowire FETs

In this article, we present a detailed analysis of the dependence of hot-carrier (HC) induced damage on the device design parameters in silicon-on-insulator (SOI) gate-all-around (GAA) nanowire (NW) n-field-effect transistors (FETs). Particularly, the HC reliability of NWs at extremely small (5 nm) to large (40 nm) widths is assessed for devices with different gate lengths. A substantial improvement in device reliability is observed at smaller NW widths, which could be due to the quantization effects and reduced effective stress voltages due to the increase in source/drain resistance. The difference in prestress device parameters, such as threshold voltage and source/drain resistance, is shown to affect the HC degradation (HCD) by altering the actual stress voltages applied to the device. Further, the impact of self-heating on the HCD mechanism is studied for devices with different fin density and gates per active region. Consequently, an empirical model is extracted using the measurement results where the empirical prefactors accurately capture the degradation in deeply scaled GAA-NWFETs.