< Terug naar vorige pagina

Publicatie

High-gain and power-efficient dynamic amplifier for pipelined SAR ADCs

Tijdschriftbijdrage - Tijdschriftartikel

© The Institution of Engineering and Technology 2017. A new power-efficient dynamic residue amplifier for pipelined successive-approximation-register (SAR) ADCs is presented. A complementary input pair and a reference level detection technique are proposed to improve the performance of the dynamic amplifier. At a 400 MS/s sampling rate, the proposed amplifier achieves a gain of 16. The input referred noise is 57.2 μV and the total harmonic distortion is –57.1 dB. The power consumption of the proposed amplifier is 55.6 μW in 28 nm CMOS technology.
Tijdschrift: Electronics Letters
ISSN: 0013-5194
Issue: 23
Volume: 53
Pagina's: 1510 - 1511
Jaar van publicatie:2017
BOF-keylabel:ja
IOF-keylabel:ja
BOF-publication weight:0.5
CSS-citation score:1
Authors from:Higher Education
Toegankelijkheid:Open