Iterating Von Neumann's post-processing under hardware constraints

© 2016 IEEE. In this paper we present a design methodology and hardware implementations of lightweight post-processing modules for debiasing random bit sequences. This work is based on the iterated Von Neumann procedure (IVN). We present a method to maximize the efficiency of IVN for applications with area and throughput constraints. The resulting hardware modules can be applied for post-processing raw numbers in random number generators.

ISBN:9781467388252

Jaar van publicatie:2016

BOF-keylabel:ja

IOF-keylabel:ja

Authors from:Government, Higher Education