III-V Nanowire Epitaxy for Ultimate Logic Device Scaling KU Leuven
This Ph.D study focuses on how to grow high yield and good quality InAs nanowires in a controllable way by selective area epitaxy on Si (111) substrate for vertical gate-all-around MOSFET applications. We first identify the challenge of direct epitaxy of InAs on Si. Gallium is found to be beneficial for the nanowire yield improvement and a new method using InGaAs nucleation layer is proposed. The distribution of planar defects in InAs ...