Development of Reliable Gate Stacks for Stacked MOS Devices in a 3D Sequential Integration KU Leuven
In order to continue increasing the circuit functionality per area, a novel concept has been envisioned which consists of stacking transistors on top of each other sequentially in the same front-end process flow (“3D Sequential Integration”). This approach would enhance device density per chip area, without requiring further reduction of the device dimensions. Additional potential advantages include a simplified co-integration of ...