High-Speed, High-Resolution CMOS Analog-to-Digital Converters KU Leuven
The continuous need for higher data rates and low power dissipation for next-generation communication standards calls for innovation in the design of extremely high-speed analog-to-digital converters (ADCs), exceeding 10 GS/s, while maintaining a medium-to-high resolution. Although complex time interleaving ADCs are a partial solution for this demand, the ADC analog front-end remains a speed bottleneck under power constraints. Moreover, even ...