Area-selective deposition mechanisms when pattern dimensions reach the nanoscale KU Leuven
The manufacturing processes for nano-electronic logic and memory devices are becoming increasingly complex due to the miniaturization of device dimensions, introduction of new materials, and the use of new device architectures/concepts that involve three dimensional (3D) structures to reduce the active footprint. For example, the Complementary Field Effect Transistor (CFET) is proposed for the ultimate scaling of logic devices. It consists of ...