Strength and Reliability Characterization of Multi-Level Back-End-of-Line under Chip Package Interaction Loading KU Leuven
With the ever increasing demands for improved performance of ICs, new reliability challenges are arising with the increasing complexity of the interconnect layer, which consists not only of reduction of dimensions, but also the introduction of new materials. One of the main goals of the semiconductor industry is to increase the speed of ICs (both Front-End-Of-Line and Back-End-Of-Line), by reducing the RC delay. While the downscaling ...