Publications
Cryogenic temperature DC-IV measurements and compact modeling of n-channel bulk FinFETs with 3–4 nm wide fins and 20 nm gate length for quantum computing applications Vrije Universiteit Brussel
CMOS circuits for Quantum Computing applications require FETs operating at cryogenic temperatures. In this work, we aim to present one of the first insights on the ability of the industry standard compact model BSIMCMG in capturing low temperature device physics. We have performed wafer-level DC-IV measurements on multi-fin n- channel bulk FinFETs with 3–4 nm wide fins and down to 20 nm designed gate length across a range of temperatures ...
Concurrent effects of wafer temperature and oxygen fraction on cryogenic silicon etching with $SF_{6}/O_{2}$ plasmas University of Antwerp
Er3+-to-Yb3+ and Pr3+-to-Yb3+ energy transfer for highly efficient near-infrared cryogenic optical temperature sensing KU Leuven Ghent University
Fluorinesilicon surface reactions during cryogenic and near room temperature etching University of Antwerp
Performances under saturation operation of p-channel FinFETs on SOI substrates at cryogenic temperature KU Leuven
In-depth static and low-frequency noise characterization of n-channel FinFETs on SOI substrates at cryogenic temperature KU Leuven
Twinning-induced strain hardening in dual-phase FeCoCrNiAl0.5 at room and cryogenic temperature KU Leuven
Reliability and Variability of Advanced CMOS Devices at Cryogenic Temperatures Vrije Universiteit Brussel
In this work, we present time-zero variability and degradation data obtained from a large set of on-chip devices in specifically designed arrays, from room temperature to 4K. We show that the investigated nMOS transistors still suffer from significant PBTI and HC degradation down to the lowest temperatures. We further investigate the contribution of multiple-carrier mechanism versus single-carrier mechanism of Si-H bond dissociation across ...