Patents

A back contact photovoltaic cell is provided, the photovoltaic cell comprising at a rear side of a silicon substrate an emitter region at first predetermined locations and a back surface field region at second predetermined locations, wherein the emitter region and the back surface field region are field induced regions. The emitter region is induced by a first layer stack comprising a passivating tunneling layer and a first transparent conductive layer with a first, e.g. high, work function, the first layer stack being provided on the rear surface of the silicon substrate at the first ...

A vertical tunneling field effect transistor (TFET) and method for forming a vertical TFET is disclosed. The vertical TFET comprises a vertical core region, a vertical source region, a vertical drain region and a gate structure. The vertical core region extends perpendicularly from a semiconductor substrate, has a top surface, consists of a doped outer part and a middle part. The vertical source region of semiconducting core material comprises the doped outer part of the vertical core region. The vertical drain region of semiconducting drain material comprises along its longitudinal direction ...

A semiconductor device comprising: i. a first structure (100) made of a first doped semiconductor material of a first doping type, ii. a metal (300) in contact with the first structure (100), and iii. at least a second structure (200) made of a second doped semiconductor material of the first doping type in contact with the first structure (100), wherein a band off-set for majority charge carriers between the first doped semiconductor material and the second doped semiconductor material is sufficiently large for charge carriers from the second doped semiconductor material to be transferred ...

Disclosed is a device, comprising: a first interconnection level (110) including a first dielectric layer (112) and a first set of conductive paths (111) arranged in the first dielectric layer, a second interconnection level (120) arranged on the first connection level and including a second dielectric layer (122) and a second set of conductive paths (121) arranged in the second dielectric layer, a third interconnection level (130) arranged on the second interconnection level and including a third dielectric layer (132) and a third set of conductive paths (131) arranged in the third ...

An optical sensor (100) comprises stacked layers comprising: a window layer (101) which allows the passage of photons (200); a sensing layer (102) for generating charges upon impinging of the photons through the window layer (101); and a bottom electrode layer (103) comprising at least one bottom electrode (105) for receiving charges generated in the sensing layer (102). The sensing layer (102) is sandwiched between the window layer (101) and the bottom electrode layer (103). The at least one bottom electrode (105) of the bottom electrode layer (103) comprises conductive material with ...

The disclosed technology relates generally to magnetic random access memory, and more particularly to spin-orbit-torque (SOT) magnetoresistive random access memory (MRAM). According to an aspect, a MRAM device comprises a first transistor, a second transistor, and a resistive memory element. The resistive memory element comprises a magnetic tunnel junction (MTJ) pillar arranged between a top electrode and bottom electrode having a first terminal and a second terminal. According to another aspect, a method of using the MRAM device is disclosed.

A semiconductor thin-film transistor, TFT, stack (200) is provided. The stack (200) includes a first TFT structure and a second TFT structure. A same metal layer (232, 233) is configured as both i) a gate metal (232) of one of the first TFT structure and the second TFT structure, and ii) a source-drain metal (232, 233) of the other one of the first TFT structure and the second TFT structure. A display of an active matrix LED type is also provided. The display includes a plurality of pixels and, for each pixel, a pixel driving circuit formed at least partly by the disclosed semiconductor TFT ...

A method of creating a doped layer at a rear side (112) of a crystalline silicon bifacial solar cell is provided, including texturing at least a rear side (114) of a silicon substrate (110) of the solar cell to create a pattern of pyramids (120), thereby creating a pyramidal topology of the rear side; forming at the rear side by epitaxial growth at least one doped silicon epitaxial layer (130) on the pyramids, and, simultaneously with forming the doped layer and by using facet evolution, the pyramidal topology of the rear side is smoothed by the growth of the epitaxial layer, and wherein the ...

A stator or a rotor for use in an electrical machine, the stator or rotor comprising a composite element comprising a rigid mass (102) suitable for comprising at least one magnetostrictive electrode bar, at least one magnetostrictive electrode bar and a piezoelectric material (106) in between said rigid mass material and said magnetostrictive electrode bars (104). The rigid mass (102), the magnetostrictive electrode bars (104) and the piezoelectric material (106) are arranged such that applying a voltage between the rigid mass (102) and one or more magnetostrictive electrodes, causes ...

A method for forming a passivating electrical contact to a crystalline semiconductor substrate is provided, the method comprising: depositing an initial intrinsic amorphous silicon-containing layer on a surface of the crystalline silicon substrate; depositing a first metal layer on the initial intrinsic amorphous silicon-containing layer; and performing an annealing process at a temperature in the range between 70°C and 200°C, thereby inducing a silicidation reaction between at least part of the first metal layer and part of the initial intrinsic amorphous silicon-containing layer and forming ...