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Researcher
Marian Verhelst
- Disciplines:Nanotechnology, Sensors, biosensors and smart sensors, Other electrical and electronic engineering, Design theories and methods
Affiliations
- Electronic Circuits and Systems (ECS) (Division)
Member
From1 Aug 2020 → 30 Sep 2022 - ESAT - MICAS, Microelectronics and Sensors (Division)
Member
From1 Dec 2007 → 31 Jul 2020 - Department of Electrical Engineering (ESAT) (Department)
Member
From1 Oct 2003 → 30 Nov 2007
Projects
1 - 10 of 60
- Explore chiplet-based processors that can be easily integrated together / tiled in a heterogeneous wayFrom29 Apr 2024 → TodayFunding: Own budget, for example: patrimony, inscription fees, gifts
- HW/SW Co-Design of Scalable ML Multi-Core Processor for Large Scale DNN ModelsFrom23 Apr 2024 → TodayFunding: Own budget, for example: patrimony, inscription fees, gifts
- Bringing generative AI to edge devices through interoperable heterogeneous compute coresFrom5 Mar 2024 → TodayFunding: Own budget, for example: patrimony, inscription fees, gifts
- Digital in memory compute for low energy biomedical machine learning applicationsFrom23 Nov 2023 → TodayFunding: Own budget, for example: patrimony, inscription fees, gifts
- Scalable large array nanopore readouts for proteomics and next-generation sequencingFrom2 Oct 2023 → TodayFunding: Own budget, for example: patrimony, inscription fees, gifts
- Efficient scheduling and compilation of embedded multi-core AI platformsFrom1 Sep 2023 → TodayFunding: Own budget, for example: patrimony, inscription fees, gifts
- Efficient multi-core processor design for heterogeneous AI workloadsFrom7 Aug 2023 → TodayFunding: Own budget, for example: patrimony, inscription fees, gifts
- Outplaying the hardware lottery for embedded AIFrom1 Jun 2023 → TodayFunding: Horizon Europe - European Research Council (ERC)
- System-Technology Co-optimization for enablement of MRAM-based Machine LearningFrom25 May 2023 → 7 Mar 2024Funding: Own budget, for example: patrimony, inscription fees, gifts
- Design Automation and Exploration for Energy Efficient Machine Learning SoCs and ChipletsFrom31 Jan 2023 → TodayFunding: Own budget, for example: patrimony, inscription fees, gifts
Publications
31 - 40 of 231
- A Flexible End-to-End Dual ASIC Transceiver for OFDM Ultrasound In-Body Communication(2022)
Authors: Thomas Bos, Marian Verhelst, Wim Dehaene
Pages: 21 - 25 - DPU: DAG Processing Unit for Irregular Graphs With Precision-Scalable Posit Arithmetic in 28 nm(2022)
Authors: Nimish Shirishbhai Shah, Shirui Zhao, Wannes Meert, Marian Verhelst
Pages: 1 - 11 - TinyVers: A 0.8-17 TOPS/W, 1.7 μW-20 mW, Tiny Versatile System-on-chip with State-Retentive eMRAM for Machine Learning Inference at the Extreme Edge(2022)
Authors: Vikram Jain, Jaro De Roose, Linyan Mei, Marian Verhelst
Number of pages: 2 - A Procedural Method to Predictively Assess Power-Quality Trade-Offs of Circuit-Level Adaptivity in IoT Systems(2022)
Authors: Marian Verhelst
- Fair and Comprehensive Benchmarking of Machine Learning Processing Chips(2022)
Authors: Marian Verhelst
Pages: 18 - 27 - Taxonomy and Benchmarking of Precision-Scalable MAC Arrays Under Enhanced DNN Dataflow Representation(2022)
Authors: Linyan Mei, Marian Verhelst
Pages: 2013 - 2024 - DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC(2022)
Authors: Kodai Ueyoshi, Pouya Houshmand, Giuseppe Sarda, Vikram Jain, Marian Verhelst
Number of pages: 3 - Enabling real-time object detection on low cost FPGAs(2022)
Authors: Vikram Jain, Marian Verhelst
Pages: 217 - 229 - Optimizing Accelerator Configurability for Mobile Transformer Networks(2022)
Authors: Steven Colleman, Marian Verhelst
Pages: 142 - 145Number of pages: 4 - A Uniform Latency Model for DNN Accelerators with Diverse Architectures and Dataflows(2022)
Authors: Linyan Mei, Marian Verhelst
Pages: 220 - 225
Patents
1 - 3 of 3