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Researcher
Cor Claeys
- Disciplines:Nanotechnology, Design theories and methods
Affiliations
- Assiocated Division ESAT-INSYS (INSYS), Integrated Systems (Division)
Member
From1 Aug 2020 → 30 Sep 2020 - Associated Section of ESAT - INSYS, Integrated Systems (Division)
Member
From19 Nov 2007 → 31 Jul 2020 - Department of Electrical Engineering (ESAT) (Department)
Member
From1 Oct 1999 → 18 Nov 2007
Publications
11 - 20 of 455
- Low-Frequency Noise in Vertically Stacked Si n-Channel Nanosheet FETs(2020)
Authors: Cor Claeys
Pages: 317 - 320 - Device Performance as a Metrology Tool to Detect Metals in Silicon(2019)
Authors: Cor Claeys
- Comparison between proton irradiated triple gate SOI TFETS and finfets from a TID point of view(2019)
Authors: Cor Claeys
- Low-Frequency Noise Assessment of Work Function Engineering Cap Layers in High-k Gate Stacks(2019)
Authors: Cor Claeys
Pages: N25 - N31 - Gate Metal and Cap Layer Effects on Ge nMOSFETs Low-Frequency Noise Behavior(2019)
Authors: Cor Claeys
Pages: 1050 - 1056 - DEFECT ASSESSMENT IN AIN NUCLEATION LAYERS GROWN ON SILICON AND SILICON-ON-INSULATOR SUBSTRATES(2019)
Authors: Cor Claeys
Number of pages: 3 - Device-Based Threading Dislocation Assessment in Germanium Hetero-Epitaxy(2019)
Authors: Cor Claeys
Number of pages: 6 - Advanced CMOS Integration Technologies for Future Mobile Applications(2019)
Authors: Cor Claeys
Number of pages: 7 - Can we optimize the gate oxide quality of DRAM input/output pMOSFETs by a post-deposition treatment?(2019)
Authors: Cor Claeys
- TaN Versus TiN Metal Gate Input/Output pMOSFETs: A Low-Frequency Noise Perspective(2018)
Authors: Cor Claeys
Pages: 3676 - 3681