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Synthesis and transfer of high-quality single-layer graphene

Book - Dissertation

Graphene, the wonder material, started 2-dimensional (2D) material interest in 2004. In that year, Geim and Novoselov were the first to isolate and characterize a single graphene sheet. Graphene itself is an atomically thin sheet of sp2-hybridized carbon atoms, which are organized in a honeycomb lattice. This crystalline structure gives rise to extraordinary mechanical properties, finding applications in the field of composites, medicine and aviation. Even more important is graphene's unique electronic structure. Each carbon atom in the graphene lattice possesses a free electron, which is not employed in lattice formation, and is allowed to freely move around the graphene hybridized zone. The large interest in graphene in the field of electronics, photonics, sensors, etc. emerges from the ballistic transport in perfect graphene. Graphene's properties have been studied in depth over the past 15 years, mainly by mechanically exfoliating graphene flakes from highly oriented pyrolytic graphite (HOPG) precursors, i.e. much like the original synthesis by Geim and Novoselov. However, this highly pure, ordered precursor only yields flakes with dimensions up to a few tens of microns, and is therefore not suitable to be introduced in the existing semiconductor (CMOS) technology. The main challenge in this thesis is to evolve towards a CMOS compatible graphene integration route. A first step in the integration is the fabrication and subsequent transfer of a single graphene sheet and is studied in this thesis. The emphasis during graphene synthesis and transfer lies on low defect density and scalability. The easiest way to introduce graphene in the semiconductor industry would be the direct deposition of graphene on top of device wafers. However, this approach is too simplistic and the obtained graphene sheets are of low quality due to the limited allowed thermal budget (< 450 °C in BEOL). High-quality graphene sheets (i.e. graphene sheets with a minimal disruption of the conjugated system and the minimization of graphene grain boundaries) need to be synthesized at much higher growth temperatures (~1000 °C) on catalytic templates. During this chemical vapor deposition (CVD) process, carbon containing precursor gases (CH4, C2H2,...) dissociate on the catalytic surface by releasing hydrogen. Since every catalyst has its unique properties (e.g. melting point, carbon solubility,...) some candidates are more suitable for the growth of high-quality single-layer graphene (Pt, Cu and Ge). This thesis focuses on the growth of single-crystalline graphene on Pt and Cu templates. Moreover, a systematic study has been performed to evaluate the nucleation behavior, number of graphene layers as well as the quality as a function of growth temperature, carbon doses and reactor pressure. As-grown graphene is characterized using scanning electron microscopy (SEM), atomic force microscopy (AFM), scanning tunneling microscopy (STM), low energy electron diffraction (LEED) and Raman spectroscopy. 'Perfect' graphene sheets constitute of a perfect hexagonal lattice of sp2-hybridized carbon atoms, which is reflected in the absence of a defect related Raman peak. In addition, the size, shape and relative orientation of graphene islands can be evaluated using SEM, STM and LEED, or by oxidation of the template (in case of Cu). Different Pt surfaces are studied and the relation between the crystal orientation and graphene growth behavior is explored. Single-layer graphene formation on Pt foils is not straightforward due to the dependency of graphene nucleation behavior on the Pt grain orientation. In addition, metallic foils in general are unfavorable due to their high roughness. Therefore, the preferred Pt template is found in a thin (500nm) Pt(111) film, deposited on OH-terminated c-plane sapphire wafers. These template wafers are atomically flat, and a minimal amount of Pt grain boundaries is observed because of the epitaxial relationship between Al2O3(0001) and Pt(111). After optimization of the growth parameters, graphene crystals on Al2O3(0001)/Pt(111) measuring up to 7mm in diameter are obtained, which exceed the current state-of-the-art. These large crystals are synthesized at high growth temperatures, and low CH4:H2 gas flow ratios. Also Al2O3(0001)/Cu(111) template wafers are evaluated as possible candidates for high-quality graphene growth. The Cu film orients itself to an untwinned single-crystalline Al2O3(0001)/Cu(111) form after annealing at 1000 °C. It is proven that the OH surface termination of sapphire and the minimum delay between cleaning and Cu sputter deposition are the most important parameters in obtaining untwinned Cu(111). A closed graphene layer, decorated with bilayer islands was formed on Al2O3(0001)/Cu(111) in a CH4:H2:Ar atmosphere. Argon was introduced in the reaction chamber to suppress Cu sublimation at the growth temperatures. An absolute minimal growth temperature of 850 °C is defined to yield graphene with a low defect density (Raman D-peak < 0.2%, corresponding to a defect density < 25 × 10^9 cm–2). The experimental data were put in perspective to some of the multilayer growth models and the bilayer nucleation could be explained by a combination of a penetration mechanism and an adsorption-diffusion mechanism. Also, a strong enhancement of the 2D-peak is observed on bilayer islands, describing the presence of turbostratic stacked graphene with relatively high rotation angles. The next challenge is the delamination of the synthesized graphene sheet from the growth substrate in order to be able to transfer the graphene layer to a target wafer. This physical separation can be performed by either etching the growth substrate, or by peeling graphene from its growth substrate. Because graphene delamination from Cu substrates is influenced by oxidation, we studied the delamination mechanisms of graphene on Pt substrates. It is shown that water intercalation plays a crucial role in changing the Pt/graphene interface. Once water intercalation occurred at the interface, a pathway for rapid ion intercalation is formed, which makes graphene delamination feasible. It is found that this ion intercalation is also dependent on the actual ions, as well as the applied external charge. The applied charge determines whether cations or anions are attracted through the water channel, while the eventual potential determines reduction-oxidation reaction processes at the edge of graphene. Graphene delamination is not observed for reactive protons and hydroxides, since these reduce/oxidize to non-charged gaseous species at the electrode under electrochemical conditions. Therefore, alkali metal and tetraalkylammonium cations as well as nitrate, sulfate and halide anions are suitable candidates for graphene delamination. The next step in the transfer process is graphene lamination on a target wafer. A lamination study on substrates with different surface potentials is performed. The usage of apolar solvents in combination with graphene on hydrophobic substrates often results in scrolling of graphene due to solvent intercalation at the graphene/substrate interface. In this work, a possible workaround is found in the direct transfer of graphene to hydrophobic wafers, where the graphene sheet was directly bonded to the target wafer. The subsequent water-based ion intercalation occurs at the growth template/graphene interface, and simultaneously avoided at the graphene/target interface. This mechanism, although challenging due to the low adhesion between graphene and hydrophobic target wafers, shows a pathway towards the control of the graphene/target interface and avoids graphene scrolling. To conclude, this work contributes to the manufacturability of graphene for applications. A complete integration route is presented, which is divided in a graphene synthesis method on Pt and Cu, and a subsequent graphene transfer process to the final device wafer. The delamination step is the most challenging step in graphene transfer processes and remains the main bottleneck for graphene integration in the existing semiconductor technology. A deeper understanding of this graphene delamination process is valuable to come to a CMOS compatible 2D material transfer process.
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