Gate stack thermal stability and PBTI reliability challenges for 3D sequential integration: demonstration of a suitable gate stack for top and bottom tier nMOS

© 2017 IEEE. 3D Sequential integration has been envisioned to stack transistors in the same front-end process. A crucial challenge is the management of the thermal budget. This work focuses on Si nMOS gate stack challenges, specifically: for a top tier device, by inserting a thin LaSiOxinterlayer between SiO2and HfO2a sufficient PBTI reliability is demonstrated without resorting to unsuitable high temperature anneals. This gate stack also offers good thermal stability for a pMOS over nMOS scenario.

ISBN:9781509066407

Publication year:2017

BOF-keylabel:yes

IOF-keylabel:yes

Authors from:Government, Higher Education