FPGA Accelerators for Cryptography and Their Protection in the Cloud

FPGA-accelerated computing has received significant attention over the last several years. It offers adaptability of hardware to application requirements and custom accelerators to various computation domains, either in embedded devices or in data-centre scale platforms. For security and cryptography applications, FPGAs allow many-times accelerated computation. Greater acceleration is possible with well-designed accelerators that optimally use the FPAG's programmable resources. Hence, such designs contain a valuable Intellectual Property (IP). For protecting the IPs from malice, the FPGAs employ security features; however, they are not yet well adapted to cloud use cases. The goal of this thesis is twofold. In the first part, we focus on FPGA-based cryptographic hardware in both embedded devices and cloud-scale platforms. We investigate how to get the maximum benefit from the programmable resources for a given hardware design and how to interact fast with the design. In the second part, we examine the FPGA's existing IP protection mechanisms with a particular interest in trusted computing with FPGAs in the cloud. We investigate the proposed and required modifications for such purposes through a literature survey, discuss potential improvements, and lastly, describe our proposed protection scheme.

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