< Back to previous page


A 13.5-Gb/s 5-mV-Sensitivity 26.8-ps-CLK–OUT Delay Triple-Latch Feedforward Dynamic Comparator in 28-nm CMOS

Book Contribution - Book Chapter Conference Contribution

We present a three-stage triple-latch feedforward fully dynamic comparator, with an achievable data rate of 13.5 Gb/s and a BER < 10^-12 for input amplitudes as small as 5 mV pp-diff . The combination of a high gain three-stage configuration and an extra parallel feedforward path results in a maximum CLK-OUT delay of only 26.8 ps and a delay slope of 6.4 ps/decade. Furthermore, the cascaded triple-latch architecture with minimized stacking enables a < 70 ps delay across a wide common-mode (Vcm) and supply (Vdd) range. The prototype comparator in 28 nm bulk CMOS dissipates 2.2 mW at 13.5 Gb/s and 5 mV pp-diff from a 1-V supply, for a core area of 78 μm^2
Book: IEEE Solid State Circuits Letters
Pages: 167 - 170
Number of pages: 4
Publication year:2019
Authors from:Higher Education