A 13.5-Gb/s 5-mV-Sensitivity 26.8-ps-CLK–OUT Delay Triple-Latch Feedforward Dynamic Comparator in 28-nm CMOS

We present a three-stage triple-latch feedforward fully dynamic comparator, with an achievable data rate of 13.5 Gb/s and a BER < 10^-12 for input amplitudes as small as 5 mV pp-diff . The combination of a high gain three-stage configuration and an extra parallel feedforward path results in a maximum CLK-OUT delay of only 26.8 ps and a delay slope of 6.4 ps/decade. Furthermore, the cascaded triple-latch architecture with minimized stacking enables a < 70 ps delay across a wide common-mode (Vcm) and supply (Vdd) range. The prototype comparator in 28 nm bulk CMOS dissipates 2.2 mW at 13.5 Gb/s and 5 mV pp-diff from a 1-V supply, for a core area of 78 μm^2

ISBN:978-1-7281-1550-4

Publication year:2019

BOF-keylabel:yes

IOF-keylabel:yes

Authors from:Higher Education

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