A 0-to-35mA NMOS Capacitor-Less LDO with Dual-Loop Regulation Achieving 3ns Response Time and 1pF-to-10nF Loading Range

This paper presents a capacitor-less low-dropout voltage regulator (LDO) based on an NMOS pass transistor and a dual-loop regulation. The first capacitively-coupled loop responds to a fast change of load currents, whereas the second time-based loop provides a high-precision regulation without requiring an external clock. Our proposed LDO, implemented in a 55nm CMOS, achieves a 3ns response time and a 240mV undershoot voltage when a large transient load step of 0-35mA and 2ns edge time is applied. Moreover, our design is stable over a wide range of capacitive (1pF to 10nF) and current loads (0 to 35mA) while consuming 16 similar to 35 mu A and an active chip area is 0.097mm(2).

Publication year:2023