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Project

Ultra energy efficient digital circuits through near/sub-threshold operation and dynamic modulation of the minimum energy point.

In today's electronic landscape, energy efficiency has become one of the key design parameters. This is driven by our desire for more powerful and capable, yet smaller and lighter portable electronic devices which preferably operate indefinitely on their battery or other limited energy sources. Within these devices, digital integrated circuits often fulfill a key role as the brain of the device and consume a significant part of the total energy consumption.

For digital circuits, voltage scaling is an effective and generic method to improve their energy efficiency. When applying this optimally, it allows digital circuits to operate in their minimum energy point (MEP) that is located at near-threshold (NT) supply voltages. Here, the dynamic and leakage energy reach their optimal trade-off point. However, only very few digital circuits exploit their MEP to reach the best energy efficiency because operating at NT voltages proves to be challenging. Four major challenges can be identified. (1) A lack of support for the NT regime from both the technology vendors and the digital implementation tools. This results in missing NT standard-cell (std-cell) models and pitfalls during an NT implementation flow. (2) A lower relative noise margin, which can cause the nominal std-cells to fail at NT voltages. (3) A conflict between the energy optimal clock frequency in the MEP and the desired clock frequency set by the application. (4) An increased impact from process, voltage and temperature variations due to the exponential nature of the NT regime that results in growing design margins which undermine the MEP's energy efficiency.

This thesis has as goal to enable efficient and reliable operation of digital circuits in their MEP at NT voltages by overcoming these challenges.

It tackles the first challenge by setting up a run-time optimized std-cell characterization flow that generates the missing NT std-cell models. Further, it provides a set of guidelines to deal with the pitfalls during the implementation flow. Next, to overcome challenges two and three, it explores the advantages offered by an FDSOI technology over a typical bulk technology. This shows that FDSOI provides a better noise margin at NT voltages and that its large body-biasing range can be leveraged to match the MEP frequency with the application frequency. A first prototype implementation uses this technology and the aforementioned characterization flow and guidelines to make a first NT implementation. The measurements of this prototype show that the FDSOI std-cells remain indeed functional at NT voltages and that body-biasing allows to optimize the dynamic versus leakage energy trade-off individually at any frequency.

Next, to overcome the final challenge, this thesis focuses strongly on design margin reduction techniques. To that end, it analyses existing error detection and correction (EDaC) systems that are capable of recovering all design margins. Based on this analysis, this work proposes a novel EDaC technique that uses completion detection (CD) to instantaneously determine the possibility of late-arriving signals. The resulting CD EDaC system does not require any additional hold constraints, can monitor paths towards any sort of endpoint, detects all critical activity in its detection window, obtains a high insertion rate, and can operate at or beyond the first point of failure.

The second prototype puts the novel CD EDaC system to the test and proves that it operates as expected. The system recovers all voltage margin at NT voltages and reclaims 69% of the energy otherwise lost in design margins. At the same time, it only infers a 6% area overhead in the processor's core area. The third and final prototype implements an improved version of the CD EDaC system. This further lowers the area overhead of the detection by 50% while using an even wider detection window and higher insertion rate. Now, the measurement results show that 82% of the energy losses caused by design margins are recovered. This leaves only a 12% overhead with respect to the ideal critical operation point of the processor.

By taking on the four NT challenges with three prototypes, this thesis proves that it is possible to use the existing std-cells for NT implementations that target the MEP. Further, the introduction of a new EDaC concept reliably safeguards the MEP's efficiency from the large NT design margins without inferring a large overhead.

Date:24 Aug 2015 →  18 Oct 2021
Keywords:Ultra energy efficient digital circuits, minimum energy point, near/sub-threshold
Disciplines:Nanotechnology, Design theories and methods
Project type:PhD project