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Reliability Characterization of Gate-stacks for III-V Channel MOSFETs

The continuous scaling of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) dimensions for over more than 5 decades has enabled the steady increase of transistor performance and density, while reducing the relative cost. These factors led to a tremendous growth of the semiconductor industry and it is remarkable that Silicon has always been the preferred channel material.

The journey of scaling Si-channel-based MOSFETs was challenging due to a myriad of issues such as short channel effects, and gate-oxide scaling limit, and in particular, low drive current. Many were overcome with clever engineering solutions, even leading to a commercially available 7nm CMOS technology node (anno 2019). However, MOSFETs for mobile applications needed to deliver high drive current at low operating voltage (low-power). To this end, alternative channel materials with high intrinsic carrier mobilities, such as InGaAs and SiGe, emerged as promising candidates. While InGaAs MOS devices with enhanced performance have already been demonstrated, their long-term Bias Temperature Instability (BTI) reliability remains a concern.

In this work, we demonstrate a gate-stack for InGaAs devices that meets all the BTI targets for DC operation, while maintaining high channel mobility (~3500 cm2/V-s) and sufficient ON-current for a 0.75V III-V technology. We also observed that BTI reliability of InGaAs devices is poorer at lower temperatures, unlike that observed in Si-channel devices, thereby implying an apparent opposite temperature activation of BTI. Novel electrical characterization techniques and semi-empirical models were developed that (i) enabled the engineering of a gate-stack with necessary electrical properties for improved BTI reliability, and (ii) provided in-depth understanding of the impact of temperature on BTI degradation.  

The poor gate-stack reliability is ascribed to the unfavorable alignment of defect energy distributions with the channel conduction band, such that a high defect density is accessible for channel carriers at low operating oxide fields. A semi-empirical model was developed which precisely estimates the oxide field dependence on the applied gate-voltage, and further calculates the effective charging defect density in order to reproduce the experimental results. This model was used to compare the defect energy distributions of different gate-stacks, and ultimately to develop a tri-layer gate-stack for InGaAs MOS devices with a more favorable alignment of defect energy distributions, necessary to meet all the BTI reliability targets.

The apparentopposite temperature activation of charge trapping in the gate-oxide was found to be specific to InGaAs devices, and hence required a more fundamental insight into the origin of the increased Vth degradation. The Non-radiative Multiphonon (NMP) theory, which describes the charge trapping process from the microscopic-physics perspective, was used to analytically model the distributions of activation energies for charge capture and emission into/from the gate-oxide defects. The activation energies were then transformed into Capture/Emission Time (CET) maps. A thorough analysis of the CET maps confirmed that the increased Vth degradation at lower temperatures is the result of different properties associated with the multiple sub-populations of oxide defects, active in the measurement range. We further concluded that such an analysis is essential for an accurate estimation of long-term BTI degradation under both DC and AC operating conditions, while also providing us with a robust semi-empirical modelling tool that has a direct association with the microscopic mechanisms causing BTI.

Date:1 Nov 2014 →  25 Feb 2019
Keywords:Semiconductor Physics, Transistor reliability, III-V Technology, Reliability Characterization
Disciplines:Nanotechnology, Design theories and methods, Condensed matter physics and nanophysics
Project type:PhD project